a) Field of the Invention
The present invention relates to manufacturing insulating films, and more particularly to a method and apparatus for manufacturing semiconductor devices having planarized insulating films.
b) Description of the Related Art
Requests for high integration and high speed operation of semiconductor IC devices are increasing more and more. In order to highly integrate semiconductor elements and operate them at a high speed, it is necessary to layout a number of semiconductor elements in a small chip area and in some cases interconnect elements by multi-layer wirings by increasing the number of wiring layers. It is desired to narrow the width of each wiring layer. The height of a wiring with a narrow width becomes greater than that of a wiring with a larger width if both the wires should have the same resistance.
The surface of a chip having such multi-layer wirings is extraordinarily irregular, so that not only the step coverage of a wiring layer formed on the chip surface but also the precision of photolithography is degraded. Therefore, planarization technique plays a more important roll in planarizing the surface of an underlying layer such as an interlayer insulating film on which a multi-layer wiring is formed.
Reflow of glasses having a softening point lowered by additive impurities, such as phosphorous silicate glass (PSG), boron silicate glass (BSG), and boron phosphorous silicate glass (BPSG), is known as one of such insulating film planarization techniques. Glass reflow technique requires a relatively high temperature so that its use is restricted and cannot be applied to semiconductor chips having a wiring with low resistance to heat such as Al or a highly precise impurity profile.
Lower temperature planarization technique has been desired. Silicon oxide film deposition technique by reacting tetraethylorthosilicate (TEOS) with ozone, can be used at a relatively low temperature and has a self-planarization function of reducing steps on the surface of an underlying layer. Although a region between convexities having a relatively narrow span can be efficiently filled with an ozone-TEOS oxide film, the planarization performance is lowered at a region between convexities having a wider span.
A silicon oxide film made from spin-on-glass (SOG) can be formed by spin-coating liquid phase silicon compound at a room temperature and annealing it at an elevated temperature. This method has a good planarization performance because of use of liquid phase silicon compound. However, this oxide film is likely to contain adsorbed or residual components such as water because the substrate is exposed in the air. It is necessary for the reduction of these unnecessary components to raise an annealing temperature. A spin coating process uses a spin coater and has a poor integrity with a dry process.
The insulating property of an oxide film formed by using such a self-planarization function is generally inferior to that of a silicon oxide film formed by general chemical vapor deposition (CVD). It is however difficult for general CVD to reduce steps on the surface of a silicon oxide film because this film is deposited in conformity with the shape of an underlying layer.
An approach has been proposed therefore in which a CVD oxide film is once formed conformably on or conformal to the surface of a substrate having steps of a wiring pattern and another oxide film having a self-planarization function such as SOG is formed on the CVD oxide film. In this specification, an insulating film without or scarcely having a self-planarization function, such as a general CVD insulating film deposited on the surface and side walls of a substrate, is called a "conformable" insulating film.
Another approach has also been proposed in which an oxide film having a self-planarization function and formed on a CVD oxide film is at least partially removed, for example, by etch-back, to thereby reduce the quantity of the oxide film having a poor film quality. In a further approach, a CVD oxide film is deposited on the surface of the etched-back oxide film to seal the oxide film having a poor film quality such as an SOG oxide film.
In the case of the method of planarizing the surface of a substrate with steps by using an ozone-TEOS oxide film, it is difficult to achieve sufficient planarization if spans between convexities formed, for example, by wirings, are wide.
If the method of planarizing the surface of a substrate by using an SOG oxide film is used to obtain a finished oxide film having a good film quality, it is preferable to coat, anneal, etch back an SOG film and form a CVD oxide film on the SOG film. However, a combination of these processes elongates a turn-around time (TAT) and increases a manufacturing cost.
Furthermore, a spin coater as well as a CVD system is required, and they show a low integrity so that it is difficult to combine them into a single unit. It is difficult to avoid out-gas of an SOG oxide film which gas hinders forming electrical contacts and selective growth at the later processes.